#VCS = vcs -full64 -sverilog -timescale=1ns/1ns +vpi -l build.log -debug_access  -CFLAGS -DVCS +all
VCS = vcs -full64 -sverilog -timescale=1ns/1ns +vpi -l build.log -debug_access  +all
SIMV = 	./simv  -l simv.log


all: comp run

SIM_OPT =+ +incdir+ $(UVM_HOME)/src/dpi/uvm_dpi.cc  
comp:
	$(VCS) $(SIM_OPT)  -f ../cfg/env.f \
                 -f ../cfg/dut.f

run:
	$(SIMV) 

verdi:
	verdi -sverilog   -f ../cfg/env.f  -f ../cfg/dut.f  -ssf vcs_dump.fsdb &

clean:
	rm -rf core csrc simv* vc_hdrs.h ucli.key urg* *.log *.fsdb* novas.* verdiLog
